I mean Verilog HDL Program for Parallel In – Serial Out Shift Register is a little plain. You should glance at Yahoo’s home page and watch how they write post titles to grab viewers to click. You might add a video or a related pic or two to grab readers excited about what you’ve got to say.

I want to convert 8 bit serial data into 8 bit parallel data my code is here library IEEE; use IEEE.STD_LOGIC_1164.all; entity PAR2SER is port( din: in STD_LOGIC; clk: in STD_LOGIC; reset: in STD_LOGIC; dout: out STD_LOGIC_VECTOR(7 downto 0) ); end PAR2SER; architecture sipo_behavior_arc of PAR2SER is begin sipo: process (clk,din,reset) is variable s: std_logic_vector(7 downto 0):= '00000000'; begin if (reset='1') then s:= '00000000'; elsif (rising_edge (clk)) then s:= (din & s(7 downto 1)); end if; dout. The waveform looks somewhat strange cause the simulation includes timing: the individual bits of dout switch with some delay with respect to the positive CLK-edge (~6ns. If one takes this delay in consideration and looks at dout only at the 'next' rsising CLK-edge, then dout toggles between xAA and x55 - just as it should when din toggles with every CLK-cycle. One thing I do not understand is, that dout as std_logic_vector is displayed as 'uninitialized' every other CLK-cycle - though each individual bit of the std_logic_vector is showing a well defined logic value. Besides that the simu just shows, what one should expect from the given description. (By the way: Ser2Par would be a much more appropriate name for this component than Par2Ser).

> but i am not getting correct data. For me the wavrform looks fine: in the shift register is '01010101' or '10101010' at the rising edge of clk. What could you expect instead? BTW: do a behavioural simulation instead of this post route timing simulation. It makes things much easier and more obvious. > One thing I do not understand is, that dout as std_logic_vector is > displayed as 'uninitialized' every other CLK-cycle - though each > individual bit of the std_logic_vector is showing a well defined logic > value.

That looks really kind of strange.